Ferroelectric α-InSe Semi-floating Gate Transistors for Multilevel Memory and Optoelectronic Logic Gate.

Journal: ACS applied materials & interfaces
Published Date: Apr 23, 2025

Abstract

Progress in artificial intelligence (AI) demands efficient data storage and high-speed processing. Traditional von Neumann architecture, with space separation of memory and computing units, struggles with increased data transmission, causing power inefficiency and date latency. To address this challenge, we designed a semi-floating gate transistor (SFGT) that integrates data storage and logical operation into a single device by employing a ferroelectric semiconductor α-InSe as a semi-floating gate layer. Leveraging the ferroelectric polarization of α-InSe, the device exhibits improved non-volatile memory performance with a high program/erase ratio of 1 × 10 and reliable durability over 1000 cycles. Through the dual-gate modulation, the SFGT achieves multilevel storage function with at least seven controllable programming states and performs three types of digital logic gate operations ("AND", "NOR", and "OR") at an ultralow bias of 10 mV. Compared to traditional FGT architectures, the α-InSe-based semi-floating gate structure achieves multifunctional integration of data storage and logic computing, effectively addressing energy consumption and time delay issues in data transmission, making it highly significant for applications in data-intensive and low-power integrated circuits.

Authors

  • Yanze Song
    Guangdong Provincial Key Laboratory of Chip and Integration Technology, School of Electronic Science and Engineering (School of Microelectronics), South China Normal University, Foshan 528225, People's Republic of China.
  • Zhidong Pan
    Guangdong Provincial Key Laboratory of Chip and Integration Technology, School of Electronic Science and Engineering (School of Microelectronics), South China Normal University, Foshan 528225, People's Republic of China.
  • Chengming Luo
    Guangdong Provincial Key Laboratory of Chip and Integration Technology, School of Electronic Science and Engineering (School of Microelectronics), South China Normal University, Foshan 528225, People's Republic of China.
  • Yue Wang
    Department of Pharmacology, University of North Carolina at Chapel Hill, Chapel Hill, NC, United States.
  • Tao Zheng
    Guangzhou Institute of Energy Conversion, Chinese Academy of Sciences, Guangzhou 510640, People's Republic of China; Key Laboratory of Renewable Energy, Chinese Academy of Sciences, Guangzhou 510640, People's Republic of China. Electronic address: zhengtao@ms.giec.ac.cn.
  • Yuan Pan
    Guangdong Provincial Key Laboratory of Chip and Integration Technology, School of Electronic Science and Engineering (School of Microelectronics), South China Normal University, Foshan 528225, People's Republic of China.
  • Nabuqi Bu
    Guangdong Provincial Key Laboratory of Chip and Integration Technology, School of Electronic Science and Engineering (School of Microelectronics), South China Normal University, Foshan 528225, People's Republic of China.
  • Ruiyang Xu
    Guangdong Provincial Key Laboratory of Chip and Integration Technology, School of Electronic Science and Engineering (School of Microelectronics), South China Normal University, Foshan 528225, People's Republic of China.
  • Nengjie Huo
    Guangdong Provincial Key Laboratory of Chip and Integration Technology, School of Electronic Science and Engineering (School of Microelectronics), South China Normal University, Foshan 528225, People's Republic of China.

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