Emerging Copper-to-Copper Bonding Techniques: Enabling High-Density Interconnects for Heterogeneous Integration.
Journal:
Nanomaterials (Basel, Switzerland)
Published Date:
May 12, 2025
Abstract
As CMOS technology continues to downsize to the nanometer range, the exponential growth predicted by Moore's Law has been significantly decelerated. Doubling chip density in the two-dimensional domain will no longer be feasible without further device downsizing. Meanwhile, emerging new device technologies, which may be incompatible with the mainstream CMOS technology, offer potential performance enhancements for system integration and could be options for a More-than-Moore system. Additionally, the explosive growth of artificial intelligence (AI) demands ever-high computing power and energy-efficient computing platforms. Heterogeneous multi-chip integration, which combines diverse components or a larger number of functional blocks with different process technologies and materials into compact 3D systems, has emerged as a critical pathway to overcome the performance limitations of monolithic integrated circuits (ICs), such as limited process/material options, low yield, and multifunctional design complexity. Furthermore, it sustains Moore's Law progression for a further smaller footprint and higher integration density, and it has become pivotal for "More-than-Moore" strategies in the next CMOS technology revolution. This approach is also crucial for sustaining computational advancements with low-power dissipation and low-latency interconnects in the coming decades. The key techniques for heterogeneous wafer-to-wafer bonding involve both copper-to-copper (Cu-Cu) and dielectric-to-dielectric bonding. This review provides a comprehensive comparison of recent advancements in Cu-Cu bonding techniques. Major issues, such as plasma treatment to activate bonding surfaces, passivation to suppress oxidation, Cu geometry, and microstructure optimization to enhance interface diffusion and regrowth, and the use of polymers as dielectrics to mitigate contamination and wafer warpage, as well as pitch size scaling, are discussed in detail.
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