Artificial Optoelectronic Synapse Featuring Bidirectional Post-Synaptic Current for Compact and Energy-Efficient Neural Hardware.

Journal: Advanced materials (Deerfield Beach, Fla.)
Published Date: May 28, 2025

Abstract

Conventional hardware neural networks (HW-NNs) have relied on unidirectional current flow of artificial synapses, necessitating a differential pair of the synapses for weight core implementation. Here, an artificial optoelectronic synapse capable of bidirectional post-synaptic current (I) is presented, eliminating the need for differential synapse pairs. This is achieved through an asymmetric metal contact structure that induces a built-in electric field for directional flow of photogenerated carriers, and a charge trapping/de-trapping layer in the gate stack (h-BN/weight control layer) that can modulate the surface potential of the semiconductor channel (WSe) using electrical signals. This structure enables precise control over the direction and magnitude of injected charge. The device demonstrates key synaptic behaviors, such as long-term potentiation/depression and spike-timing-dependent plasticity. A fabricated 3 × 2 artificial synapse array shows that the bidirectional I characteristic is compatible with multiply-accumulate operations. Finally, the feasibility of these synapses in HW-NNs is demonstrated through training and inference simulations using the MNIST handwritten digits dataset, yielding competitive recognition rates and reduced total energy consumption for updating weights of the weight core compared to unidirectional I-based systems. This approach paves the way toward more compact and energy-efficient brain-inspired computing systems.

Authors

  • Hogeun Ahn
    Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, 16419, Republic of Korea.
  • Yena Kim
    Department of Mathematics, Hawaii Pacific University, 1 Aloha Tower Drive, Honolulu, HI, 96813, USA.
  • Seunghwan Seo
    Department of Electrical and Computer Engineering, Sungkyunkwan University (SKKU), Suwon, 16419, Korea.
  • Junseo Lee
    Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, 16419, Republic of Korea.
  • Sehee Lee
    Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, 16419, Republic of Korea.
  • Saeyoung Oh
    Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejeon, 34141, Republic of Korea.
  • Byeongchan Kim
    Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, 16419, Republic of Korea.
  • Jeongwon Park
    Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejeon, 34141, Republic of Korea.
  • Sumin Kang
    AgeTech-Service Convergence Major, Department of Electronic Engineering, Kyung Hee University, Yongin 17104, Republic of Korea.
  • Yuseok Kim
    Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejeon, 34141, Republic of Korea.
  • Ayoung Ham
    Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejeon, 34141, Republic of Korea.
  • Jaehyun Lee
    Department of Bio and Brain Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea.
  • Donggeon Park
    Graduate School of Semiconductor Technology, Korea Advanced Institute of Science and Technology, Daejeon, 34141, Republic of Korea.
  • Seongdae Kwon
    Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejeon, 34141, Republic of Korea.
  • Doyoon Lee
    Department of Mechanical Engineering, Massachusetts Institute of Technology, Cambridge, MA, USA.
  • Jung-El Ryu
    Department of Mechanical Engineering, Massachusetts Institute of Technology, Cambridge, MA, 02138, USA.
  • June-Chul Shin
    Department of Mechanical Engineering, Massachusetts Institute of Technology, Cambridge, MA, 02138, USA.
  • Atharva Sahasrabudhe
    Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA, USA.
  • Ki Seok Kim
    Research Laboratory of Electronics, Massachusetts Institute of Technology (MIT), Cambridge, MA, 02139, USA.
  • Sang-Hoon Bae
    Department of Mechanical Engineering and Materials Science, Washington University, Saint Louis, MO, 63130, USA.
  • Kibum Kang
    Department of Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Daejeon, 34141, Republic of Korea.
  • Jeehwan Kim
    Department of Mechanical Engineering, Massachusetts Institute of Technology, Cambridge, MA, USA. jeehwan@mit.edu.
  • Saeroonter Oh
    Department of Semiconductor Convergence Engineering, Sungkyunkwan University, Suwon, 16419, Republic of Korea.
  • Jin-Hong Park

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