NACHOS: Neural Architecture Search for Hardware-Constrained Early-Exit Neural Networks.

Journal: IEEE transactions on neural networks and learning systems
Published Date:

Abstract

Early-exit neural networks (EENNs) endow a standard deep neural network (DNN) with early-exit classifiers (EECs) to provide predictions at intermediate points of the processing when enough confidence in classification is achieved. This leads to many benefits in terms of effectiveness and efficiency. Currently, the design of EENNs is carried out manually by experts, a complex and time-consuming task that requires accounting for many aspects, including the correct placement, the thresholding, and the computational overhead of the EECs. For this reason, the research is exploring the use of neural architecture search (NAS) to automate the design of EENNs. Currently, few comprehensive NAS solutions for EENNs have been proposed in the literature, and a fully automated, joint design strategy taking into consideration both the backbone and the EECs remains an open problem. To this end, this work presents neural architecture search for hardware-constrained early exit neural networks (NACHOS), the first NAS framework for the design of optimal EENNs satisfying constraints on the accuracy and the number of multiply and accumulate (MAC) operations performed by the EENNs at inference time. In particular, this provides the joint design of backbone and EECs to select a set of admissible (i.e., respecting the constraints) Pareto optimal solutions in terms of the best trade-off between the accuracy and the number of MACs. The results show that the models designed by NACHOS are competitive with the state-of-the-art EENNs. Additionally, this work investigates the effectiveness of two novel regularization terms designed for the optimization of the auxiliary classifiers of the EENN.

Authors

  • Matteo Gambella
  • Jary Pomponi
    Department of Information Engineering, Electronics and Telecommunications (DIET), Sapienza University of Rome, Italy. Electronic address: jary.pomponi@uniroma1.it.
  • Simone Scardapane
    Department of Information Engineering, Electronics and Telecommunications (DIET), "Sapienza" University of Rome, Via Eudossiana 18, 00184 Rome, Italy.
  • Manuel Roveri
    1 Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, piazza L. da Vinci 32, Milano, 20133, Italy.

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