A Flexible Precision Scaling Deep Neural Network Accelerator with Efficient Weight Combination
Journal:
arXiv
Published Date:
Feb 2, 2025
Abstract
Deploying mixed-precision neural networks on edge devices is friendly to
hardware resources and power consumption. To support fully mixed-precision
neural network inference, it is necessary to design flexible hardware
accelerators for continuous varying precision operations. However, the previous
works have issues on hardware utilization and overhead of reconfigurable logic.
In this paper, we propose an efficient accelerator for 2~8-bit precision
scaling with serial activation input and parallel weight preloaded. First, we
set two loading modes for the weight operands and decompose the weight into the
corresponding bitwidths, which extends the weight precision support
efficiently. Then, to improve hardware utilization of low-precision operations,
we design the architecture that performs bit-serial MAC operation with systolic
dataflow, and the partial sums are combined spatially. Furthermore, we designed
an efficient carry save adder tree supporting both signed and unsigned number
summation across rows. The experiment result shows that the proposed
accelerator, synthesized with TSMC 28nm CMOS technology, achieves peak
throughput of 4.09TOPS and peak energy efficiency of 68.94TOPS/W at 2/2-bit
operations.
