Incorporating a variety of synaptic dynamics in neuromorphic hardware: different types of inhibition and plasticity.

Objective.This study aims to design a CMOS-based circuit that mimics the behavior of real brain synapses, focusing on both plasticity and inhibition. The goal is to improve the biological realism and learning ability of neuromorphic hardware.Approach.A unified CMOS-based synaptic architecture is proposed that integrates short-term plasticity (STP) and long-term plasticity (LTP) with two forms of synaptic inhibition: divisive and subtractive. The STP circuit models short-term depression and facilitation, while the LTP mechanism employs spike-timing-dependent plasticity to capture temporally driven synaptic modifications. Furthermore, a spiking neuronal network is designed to demonstrate biologically accurate inhibitory effects and to perform max pooling via divisive inhibition. All circuits are implemented and simulated in TSMC 180 nm CMOS using Cadence Virtuoso.Main results.The proposed circuits successfully reproduce key biological features of synaptic behavior. The STP and LTP blocks enable time-dependent modulation of synaptic weights, while the inhibitory networks exhibit both divisive and subtractive control over postsynaptic firing frequency. The maxpooling operation, achieved via divisive inhibition, allows the target neuron to respond to the input with the highest spiking activity selectively. Simulation results confirm the correct functional behavior of all the designed circuits.Significance.This work provides a simple and effective hardware solution for modeling fundamental synaptic functions. It supports adaptive learning and efficient processing in neuromorphic systems. The results can help build better brain-like systems for AI, robotics, and brain-computer interfaces.