Hybrid neuromorphic hardware with sparing 2D synapse and CMOS neuron for character recognition.

Journal: Science bulletin
PMID: 37714804

Abstract

Neuromorphic computing enables efficient processing of data-intensive tasks, but requires numerous artificial synapses and neurons for certain functions, which leads to bulky systems and energy challenges. Achieving functionality with fewer synapses and neurons will facilitate integration density and computility. Two-dimensional (2D) materials exhibit potential for artificial synapses, including diverse biomimetic plasticity and efficient computing. Considering the complexity of neuron circuits and the maturity of complementary metal-oxide-semiconductor (CMOS), hybrid integration is attractive. Here, we demonstrate a hybrid neuromorphic hardware with 2D MoS synaptic arrays and CMOS neural circuitry integrated on board. With the joint benefit of hybrid integration, frequency coding and feature extraction, a total cost of twelve MoS synapses, three CMOS neurons, combined with digital/analogue converter enables alphabetic and numeric recognition. MoS synapses exhibit progressively tunable weight plasticity, CMOS neurons integrate and fire frequency-encoded spikes to display the target characters. The synapse- and neuron-saving hybrid hardware exhibits a competitive accuracy of 98.8% and single recognition energy consumption of 11.4 μW. This work provides a viable solution for building neuromorphic hardware with high compactness and computility.

Authors

  • Siwei Xue
    Shanghai Key Laboratory for Future Computing Hardware and System, School of Microelectronics, Fudan University, Shanghai 200433, China.
  • Shuiyuan Wang
    Shanghai Key Laboratory for Future Computing Hardware and System, School of Microelectronics, Fudan University, Shanghai 200433, China. Electronic address: sy_wang@fudan.edu.cn.
  • Tianxiang Wu
    State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China.
  • Ziye Di
    Shanghai Key Laboratory for Future Computing Hardware and System, School of Microelectronics, Fudan University, Shanghai 200433, China.
  • Nuo Xu
    Information Engineering, Guangdong University of Technology, Guangzhou, China.
  • Yibo Sun
    Shanghai Key Laboratory for Future Computing Hardware and System, School of Microelectronics, Fudan University, Shanghai 200433, China.
  • Chaofan Zeng
    Guangzhou Institute of Technology, Guangzhou, Guangdong 510075, China.
  • Shunli Ma
    State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China.
  • Peng Zhou
    School of International Studies, Zhejiang University, Hangzhou, China.

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