An artificial neural network chip based on two-dimensional semiconductor.

Journal: Science bulletin
PMID: 36546076

Abstract

Recently, research on two-dimensional (2D) semiconductors has begun to translate from the fundamental investigation into rudimentary functional circuits. In this work, we unveil the first functional MoS artificial neural network (ANN) chip, including multiply-and-accumulate (MAC), memory and activation function circuits. Such MoS ANN chip is realized through fabricating 818 field-effect transistors (FETs) on a wafer-scale and high-homogeneity MoS film, with a gate-last process to realize top gate structured FETs. A 62-level simulation program with integrated circuit emphasis (SPICE) model is utilized to design and optimize our analog ANN circuits. To demonstrate a practical application, a tactile digit sensing recognition was demonstrated based on our ANN circuits. After training, the digit recognition rate exceeds 97%. Our work not only demonstrates the protentional of 2D semiconductors in wafer-scale integrated circuits, but also paves the way for its future application in AI computation.

Authors

  • Shunli Ma
    State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China.
  • Tianxiang Wu
    State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China.
  • Xinyu Chen
    State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China.
  • Yin Wang
    State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China.
  • Hongwei Tang
    State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China.
  • Yuting Yao
    State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China.
  • Yan Wang
    College of Animal Science and Technology, Beijing University of Agriculture, Beijing, China.
  • Ziyang Zhu
    State Key Laboratory of ASIC and System, School of Information Science and Technology, Fudan University, Shanghai 200433, China.
  • Jianan Deng
    State Key Laboratory of ASIC and System, School of Information Science and Technology, Fudan University, Shanghai 200433, China.
  • Jing Wan
    State Key Laboratory of ASIC and System, School of Information Science and Technology, Fudan University, Shanghai 200433, China.
  • Ye Lu
    State Key Laboratory of ASIC and System, School of Information Science and Technology, Fudan University, Shanghai 200433, China.
  • Zhengzong Sun
    State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China.
  • Zihan Xu
    Shenzhen Sixcarbon Technology, Shenzhen 518106, China.
  • Antoine Riaud
    State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China.
  • Chenjian Wu
    School of Electronic and Information Engineering, Soochow University, Suzhou 215006, China.
  • David Wei Zhang
    State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China.
  • Yang Chai
    Department of Applied Physics, The Hong Kong Polytechnic University, Hung Hom, Kowloon, Hong Kong, China.
  • Peng Zhou
    School of International Studies, Zhejiang University, Hangzhou, China.
  • Junyan Ren
    State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China. Electronic address: junyanren@fudan.edu.cn.
  • Wenzhong Bao
    State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China. Electronic address: baowz@fudan.edu.cn.

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